1. Field of the Invention
The invention relates generally to insulated gate field effect devices, and more particularly, to achievement of a longer effective channel length without increasing the occupying area for insulated gate field effect devices and a method of forming the same.
2. Description of the Related Art
As the high integration of semiconductor integrated circuit devices (IC) make progress, various problems arise. In insulated gate field effect devices, the following problems caused by the high integration are noted.
FIG. 6 is a sectional view showing a structure of a conventional planar insulated gate field effect device. A MOS transistor is indicated in this figure. Referring to FIG. 6, the MOS transistor comprises a n type semiconductor substrate e.g. a n type silicon substrate 6, a p+ source 4 and a p+ drain 5 each formed in the vicinity of the main surface of semiconductor substrate 6 by diffusion, a gate oxide film 22 formed on the main surface of substrate 6, and a conductive layer formed above the main surface of substrate 6 with an insulating film 22 interposed therebetween, i.e., a gate 21. A channel region 27 which is indicated by "x" in the figure is formed in the vicinity of the main surface between the source 4 and the drain 5. Since the length of the channel region will be slightly corroded by a diffusion for the formation of the source 4 and the drain 5, an effective channel length Le1 is obtained in practice.
FIG. 7 is a structural sectional view showing the development of a depletion layer in the MOS transistor of FIG. 6. Referring to FIG. 7, the source 4 and the drain 5 are grounded to make definite the development of a depletion layer. Accordingly, a depletion layer 29 is formed so as to surround the source 4 and the drain 5.
In addition, voltage V.sub.G is supplied to the gate 1 causing a depletion layer 20 with a trapezoid configuration to be formed under the gate 1 and between the depletion layers 29. In this case, the effective channel length Le1 is defined by the longer side of the trapezoid depletion layer 20. Substrate voltage V.sub.sub is supplied to the substrate 6.
FIG. 8 is a structural sectional diagram of the structure in FIG. 7 when seen from the arrow 8. Referring to FIG. 8, a depletion layer 20 having an effective channel width of We1 is formed between local oxidation of silicons (referred to as LOCOS hereinafter) 11 for element isolation.